/* Contents of Memory Array starting from address 0.  This is a standard Verilog readmemh format. */
53 46 44 50 05 01 00 ff 00 05 01 10 80 00 00 ff
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
e5 20 f9 ff ff ff ff 01 44 eb 08 6b 08 3b 42 bb
fe ff ff ff ff ff 00 00 ff ff 40 eb 0c 20 0f 52
10 d8 00 00 26 02 a6 00 81 e6 14 c9 ed 61 76 33
7a 75 7a 75 f7 a2 d5 5c 19 f7 4d ff e9 30 c0 80 
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff 
